An All-Digital PLL Proposal using Gain Control Technique

Vlademir J S Oliveira, Wagner C Mariani, Fábio V Grigollo

Abstract


Time-to-digital converter (TDC) has been the main technique used in all-digital phase-locked loops (ADPLL). However, this approach has several design issues, and the solutions to resolve them always increase the complexity of the system. In this paper, an alternative method for handle the frequency error detection using a type II ADPLL architecture is presented. The proposed technique does not perform direct conversion from time to digital, but employs the discrete-time processing of compared signals from phase error detection. This architecture has the advantage of scalability and integration of all-digital techniques and has less complexity than conventional ADPLLs. The derivation of equations for the proposed architecture and its noise analysis is provided. The results are validated through system level simulations using macro-models of the devices. The result of the transient simulation shows the theoretical predictions about the trajectory of output frequency.

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References


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